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1. #ALTERA QUARTUS II PROGRAMMER DETECT USB BLASTER HOW TO#
2. #ALTERA QUARTUS II PROGRAMMER DETECT USB BLASTER SERIAL#
3. #ALTERA QUARTUS II PROGRAMMER DETECT USB BLASTER LICENSE#

Once the RTL for Qsys system is generated, the process completion message is displayed. The window will pop up and ask to configure some of the parameters, just keep the defaults and click generate. Once the Qsys system is saved then click on the generate HDL option located at the right bottom corner. This value will be used in the further steps Take note of the epcs_flash_controller_0 base address.

#ALTERA QUARTUS II PROGRAMMER DETECT USB BLASTER SERIAL#

The pin assignment for SPI interface is automatically take care by the tool as we “s elected automatically select dedicated active serial interface” option while adding EPCS Flash controller Assign the Export pin names, as shown (only the clock and the reset pins are exported).Make connections and configure desired frequency of the system clock as shown in the diagram below In this case the system clock is configured to 50 MHz.

When this option is selected we don’t see SPI lines listed in the export section of EPCS flash controller. If “automatically select dedicated serial interface ” option is checked, then the tool is responsible for assigning dedicated FPGA pins for the SPI interface between FPGA and the SPI flash. Just keep the default settings and Click Finish.

Type EPCS in the IP catalog search bar and double click on EPCS flash controller. Next step is to add EPCS Flash controller to the Qsys system. Once vector memories are configured as shown above just click finish (Don’t change any other settings).

#ALTERA QUARTUS II PROGRAMMER DETECT USB BLASTER LICENSE#

#ALTERA QUARTUS II PROGRAMMER DETECT USB BLASTER HOW TO#

The below steps demonstrate how to create a Qsys system which contains the nios processor and the EPCS controllerĪ Qsys window pops up as shown below. After the target design to communicate to the SPI flash has been created, the resulting *.sof file can be used for all future programming. Step 1: Creating a Nios II project (Flash Programmer Target Design).Ĭreating the flash programming target/NiosII design is a one time job, it only The steps are explained assuming the reader is familiar with Altera FPGA development. In general, the procedure should apply to all other versions of Quartus II software. The method introduced in this blog was verified on the Altera Cyclone V Development Board, using Quartus II 15.1. As a final step use the Nios II command shell to program SPI flash with the.sof file which you intended to program to the external SPI flash and convert that into a. sof file generated in step 2 on to the Altera FPGA. sof (SRAM object) file for the Nios II project created in step 1. Creating a Nios II project (QSYS system which contains Nios II processor + EPCS flash controller).Here we describes an alternate method to program the SPI flashes which are not supported by the Quartus II Flash Programmer by using Altera’s Nios® II tool, which works with all versions of Quartus II software. There are some special cases in which altera programmer doesn’t work for third party SPI flash even after disabling the ID check while generating the. In such cases, users cannot use the built-in Quartus II Flash Programmer to program a JTAG Indirect File (*.jic) to the SPI flash, because the programmer checks the EPCS Device ID before initiating the programming. In an Active Serial (AS) configuration scheme, a SPI flash device can be used to configure the Altera FPGA that acts as the configuration master while the SPI flash acts as a slave.Īltera recommends using their serial configuration devices (EPCS) in the Active Serial scheme, although users may prefer to use third party SPI flash instead of EPCS devices.